Image display and horizontal speed modulator

ABSTRACT

A video signal processing circuit synthesizes a video signal and a graphic signal on the basis of a display switching control signal, inverts a synthesized signal on the time axis for each of a forward scanning period and a backward scanning period, and output a display signal. A speed modulating signal control circuit inverts the binarized display switching control signal on the time axis for each of the forward scanning period and the backward scanning period, expands the pulse width thereof, and feeds the display switching control signal to a speed modulating signal generating circuit. The speed modulating signal generating circuit subjects a display signal to first-order differentiation, inverts the polarity of a differentiated signal in the backward scanning signal, sets a portion, corresponding to the graphic signal, in the differentiated signal on the basis of the display switching control signal at a zero level, and generates a speed modulating signal.

TECHNICAL FIELD

The present invention relates to a horizontal bidirectional deflectionsystem image display which is suitable for display of a highly preciseimage.

BACKGROUND ART

In recent years, digital techniques have been developed, andparticularly the costs of large-capacity memories are reduced. Theapplications of image processing techniques using the memories havesignificantly progressed. In JP-A-8-172543, a bidirectional deflectionsystem CRT (Cathode-Ray Tube) display has been proposed in order toreduce the power consumption at a high horizontal scanning frequency.

When the bidirectional deflection system CRT display which has beenproposed in the prior art is put on the market as an actual imagedisplay such as a monitor apparatus for display or a televisionreceiver, the function of graphically displaying set contents, channels,and the like by OSD (On Screen Display) is required.

FIG. 13(a) is a diagram showing an example of display of a video signaland an OSD graphic signal in conventional forward scanning, FIG. 13(b)is a diagram showing a phase relationship among a horizontalsynchronizing signal, a video signal, a graphic signal (charactersignal), and a display switching control signal at the time of theforward scanning.

In FIG. 13(a), an ellipse on each of forward scanning lines L1, L2, andL3 indicates an on-screen display by the graphic signal. In FIG. 13(b),the video signal is outputted when the display switching control signalis at a low level, while the graphic signal is outputted when thedisplay switching control signal is at a high level. Display by thevideo signal as well as on-screen display by the graphic signal are thusperformed in each of forward scanning periods.

However, a technique for performing on-screen display in thebidirectional deflection system image display has not been established.

On the other hand, in the television receiver, a technique for enhancingthe contour of an image using a method of horizontal speed modulation toimprove focusing characteristics of a CRT has been widely employed. InJP-A-6-284309, the application of a speed modulation technique to abidirectional deflection system has been proposed.

In the bidirectional deflection system image display, however, on-screendisplay and horizontal speed modulation are difficult to perform.

Therefore, it is desired to establish a technique making on-screendisplay possible in the bidirectional deflection system image display aswell as to further establish a technique for performing horizontal speedmodulation in the bidirectional deflection system image display capableof performing such on-screen display.

An object of the present invention is to provide a bidirectionaldeflection system image display capable of performing on-screen display.

Another object of the present invention is to provide a bidirectionaldeflection system image display capable of performing on-screen displayand horizontal speed modulation.

Still another object of the present invention is to provide a horizontalspeed modulator (horizontal velocity modulator) used for a bidirectionaldeflection system image display capable of performing on-screen display.

DISCLOSURE OF INVENTION

An image display according to an aspect of the present invention is animage display for displaying an image by forward scanning and backwardscanning, comprising inverting means for inverting on the time axis avideo signal and a graphic signal which correspond to the backwardscanning; switching and outputting means for switching and outputtingthe video signal and the graphic signal which correspond to the forwardscanning and switching and outputting the video signal and the graphicsignal, which have been inverted, corresponding to the backwardscanning; and display means for displaying the video signal and thegraphic signal which have been outputted by the forward scanning and thebackward scanning.

Therefore, the video signal and the graphic signal can be displayed bythe forward scanning and the backward scanning. Consequently, abidirectional deflection system image display capable of performingon-screen display is realized.

An image display according to another aspect of the present invention isan image display for displaying an image by forward scanning andbackward scanning, comprising video signal inverting means foralternately inverting the output order of an inputted video signalbetween the forward scanning and the backward scanning; graphic signalgenerating means for generating a graphic signal; graphic signalinverting means for alternately inverting the output order of thegraphic signal generated by the graphic signal generating means betweenthe forward scanning and the backward scanning; display signal switchingmeans for switching the display of the video signal outputted from thevideo signal inverting means and the graphic signal outputted from thegraphic signal inverting means; switching and inverting means foralternately inverting the order of switching by the display signalswitching means between the forward scanning and the backward scanning;and display means for displaying the video signal and the graphic signalwhich are outputted from the display signal switching means by theforward scanning and the backward scanning.

In the image display, the output order of the inputted video signal isalternately inverted between the forward scanning and the backwardscanning, and the output order of the graphic signal is alternatelyinverted between the forward scanning and the backward scanning. Thedisplay of the video signal and the graphic signal is switched. In thiscase, the order of switching is alternately inverted between the forwardscanning and the backward scanning. Therefore, the video signal and thegraphic signal are displayed by the forward scanning and the backwardscanning.

Consequently, a bidirectional deflection system image display capable ofperforming on-screen display is realized.

An image display according to still another aspect of the presentinvention is an image display for displaying an image by forwardscanning and backward scanning, comprising synthesizing means forsynthesizing a video signal and a graphic signal which correspond to theforward scanning and the backward scanning; inverting means forinverting on the time axis the video signal and the graphic signal,which have been synthesized, corresponding to the backward scanning; anddisplay means for displaying by the forward scanning the video signaland the graphic signal, which have been synthesized, corresponding tothe forward scanning, and displaying by the backward scanning the videosignal and the graphic signal, which have been inverted, correspondingto the backward scanning.

Therefore, the video signal and the graphic signal can be displayed bythe forward scannig and the backward scanning. Consequently, abidirectional deflection system image display capable of performingon-screen display is realized.

An image display according to still another aspect of the presentinvention is an image display for displaying an image by forwardscanning and backward scanning, comprising graphic signal generatingmeans for generating a graphic signal; synthesizing means forsynthesizing an inputted video signal and the graphic signal outputtedfrom the graphic signal generating means; video signal inverting meansfor alternately inverting the output order of the video signal and thegraphic signal which have been synthesized by the synthesizing meansbetween the forward scanning and the backward scanning; and displaymeans for displaying the video signal and the graphic signal which areoutputted from the video signal inverting means by the forward scanningand the backward scanning.

In the image display, the video signal and the graphic signal which areinputted are synthesized. The output order of the video signal and thegraphic signal which have been synthesized is alternately invertedbetween the forward scanning and the backward scanning.

Therefore, the video signal and the graphic signal are displayed by theforward scanning and the backward scanning. Consequently, abidirectional deflection system image display capable of performingon-screen display is realized.

An image display according to still another aspect of the presentinvention is an image display for displaying an image by forwardscanning and backward scanning, comprising inverting means for invertingon the time axis a video signal corresponding to the backward scanning;switching and outputting means for switching and outputting the videosignal and the graphic signal which correspond to the forward scanning;masking means for masking a portion, corresponding to a displayedportion of the graphic signal in the upper or lower forward scanning, inthe video signal corresponding to the backward scanning; and displaymeans for displaying by the forward scanning the video signal and thegraphic signal which correspond to the forward scanning, and displayingby the backward scanning the video signal, which has been partiallymasked, corresponding to the backward scanning.

Therefore, the video signal and the graphic signal are displayed by theforward scanning, and the video signal whose portion corresponding tothe displayed portion of the graphic signal has been masked is displayedby the backward scanning. Consequently, a bidirectional deflectionsystem image display capable of performing on-screen display only by theforward scanning is realized.

An image display according to still another aspect of the presentinvention is an image display for displaying an image by forwardscanning and backward scanning, comprising video signal inverting meansfor alternately inverting the output order of an inputted video signalby the forward scanning and the backward scanning; graphic signalgenerating means for generating a graphic signal; display signalswitching means for switching the display of the video signal outputtedfrom the video signal inverting means and the graphic signal outputtedfrom the graphic signal generating means as well as masking a portion,corresponding to a displayed portion of the graphic signal in the upperor lower forward scanning, in the video signal corresponding to thebackward scanning with a mask signal generated by the graphic signalgenerating means; switching and inverting means for alternatelyinverting the order of switching by the display signal switching meansbetween the forward scanning and the backward scanning; and displaymeans for displaying by the forward scanning the video signal and thegraphic signal which are outputted from the display signal switchingmeans, and displaying by the backward scanning the video signal and themask signal which are outputted from the display signal switching means.

In the image display, the output order of the inputted video signal isalternately inverted between the forward scanning and the backwardscanning. Further, the display of the video signal and the graphicsignal is switched, and the portion, corresponding to the displayedportion of the graphic signal in the upper or lower forward scanning, inthe video signal corresponding to the backward scanning is masked withthe mask signal. In this case, the order of switching is alternatelyinverted between the forward scanning and the backward scanning.

Therefore, the video signal and tie graphic signal are displayed by theforward scanning, and the video signal which has been partially maskedis displayed by the backward scanning. Consequently, a bidirectionaldeflection system image display capable of performing on-screen displayonly by the forward scanning is realized.

An image display according to still another aspect of the presentinvention is an image display for displaying an image by forwardscanning and backward scanning, comprising synthesizing means forsynthesizing a video signal and a graphic signal which correspond to theforward scanning and the backward scanning; masking means for masking aportion, corresponding to a displayed portion of the graphic signal inthe upper or lower forward scanning, in the video signal correspondingto the backward scanning; inverting means for inverting on the time axisthe video signal, which has been partially masked, corresponding to thebackward scanning; and display means for displaying by the forwardscanning the video signal and the graphic signal which correspond to theforward scanning, and displaying by the backward scanning the videosignal, which has been partially masked, corresponding to the backwardscanning.

Therefore, the video signal and the graphic signal are displayed by theforward scanning, and the video signal whose portion corresponding tothe displayed portion of the graphic signal has been masked is displayedby the backward scanning. Consequently, a bidirectional deflectionsystem image display capable of performing on-screen display only by theforward scanning is realized.

An image display according to still another aspect of the presentinvention is an image display for displaying an image by forwardscanning and backward scanning, comprising graphic signal generatingmeans for generating a graphic signal; synthesizing means forsynthesizing an inputted video signal and the graphic signal outputtedfrom the graphic signal generating means; masking means receiving thevideo signal and the graphic signal which have been synthesized by thesynthesizing means, and masking a portion, corresponding to a displayedportion of the graphic signal in the upper or lower forward scanning, inthe video signal corresponding to the backward scanning and outputtingthe video signal and the graphic signal; video signal inverting meansfor alternately inverting the output order of the video signal and thegraphic signal which are outputted from the masking means between theforward scanning and the backward scanning; and display means fordisplaying by the forward scanning the video signal and the graphicsignal, corresponding to the forward scanning, which are outputted fromthe video signal inverting means, and displaying by the backwardscanning the video signal, which has been partially masked, outputtedfrom the video signal inverting means.

In the image display, the video signal and the graphic signal which areinputted are synthesized. Further, the portion, corresponding to thedisplayed portion of the graphic signal in the upper or lower forwardscanning, in the video signal corresponding to the backward scanning ismasked, to output the video signal and the graphic signal. The outputorder of the video signal and the graphic signal is alternately invertedbetween the forward scanning and the backward scanning.

Therefore, the video signal and the graphic signal are displayed by theforward scanning, and the video signal which has been partially maskedis displayed by the backward scanning. Consequently, a bidirectionaldeflection system image display capable of performing on-screen displayonly by the forward scanning is realized.

An image display according to still another aspect of the presentinvention is an image display for displaying an image by forwardscanning and backward scanning, comprising inverting means foralternately inverting the output order of a video signal and a graphicsignal between the forward scanning and the backward scanning whilesynthesizing the video signal and the graphic signal; display means fordisplaying the video signal and the graphic signal which have beenoutputted by the forward scanning and the backward scanning; generatingmeans for generating a horizontal speed modulating signal (horizontalvelocity modulating signal) by differentiating the video signal and thegraphic signal which have been outputted; and horizontal speedmodulating means (horizontal velocity modulating means) for performinghorizontal speed modulation (horizontal velocity modulation) on thebasis of the generated horizontal speed modulating signal.

In the image display, the video signal and the graphic signal aredisplayed by the forward scanning and the backward scanning, and thevideo signal and the graphic signal are differentiated so that thehorizontal speed modulating signal is generated. The horizontal speedmodulation is performed on the basis of the generated horizontal speedmodulation.

Consequently, a bidirectional deflection system image display capable ofperforming on-screen display and horizontal speed modulation isrealized.

The image display may further comprise level control means forcontrolling a portion, corresponding to the graphic signal, in thehorizontal speed modulating signal generated by the generating means ata predetermined level.

In this case, the portion, corresponding to the graphic signal, in thehorizontal speed modulating signal, is controlled, thereby making itpossible to prevent the image quality of a character portion which ison-screen displayed from being degraded.

An image display according to still another aspect of the presentinvention is an image display for displaying an image by forwardscanning and backward scanning, comprising synthesizing and invertingmeans for alternately inverting the output order of the video signal andthe graphic signal which are inputted between the forward scanning andthe backward scanning while synthesizing the video signal and thegraphic signal; display means for displaying the video signal and thegraphic signal which are outputted from the synthesizing and invertingmeans by the forward scanning and the backward scanning; horizontalspeed modulating signal generating means for differentiating the videosignal and the graphic signal which are outputted from the synthesizingand inverting means to generate the horizontal signal modulating signal;and horizontal speed modulating means for performing horizontal speedmodulation on the basis of the horizontal speed modulating signaloutputted from a horizontal speed modulating signal generating means.

In the image display, the output order of the video signal and thegraphic signal which are inputted is alternately inverted between theforward scanning and the backward scanning while the video signal andthe graphic signal are being synthesized. The video signal and thegraphic signal which have been synthesized are displayed by the forwardscanning and the backward scanning. The video signal and the graphicsignal which have been synthesized are differentiated so that thehorizontal speed modulating signal is generated. The horizontal speedmodulation is performed on the basis of the horizontal speed modulatingsignal.

Consequently, a bidirectional deflection system image display capable ofperforming on-screen display and horizontal speed modulation isrealized.

The horizontal speed modulating signal generating means may comprisedifferentiating means for differentiating the video signal and thegraphic signal which are outputted from the synthesizing and invertingmeans, and polarity inverting means for alternately inverting thepolarity of an output signal of the differentiating means between theforward scanning and the backward scanning.

The image display may further comprise horizontal speed modulatingsignal control means for controlling a portion, corresponding to thegraphic signal, in the horizontal speed modulating signal generated bythe horizontal speed modulating signal generating means.

In this case, the portion, corresponding to the graphic signal, in thehorizontal speed modulating signal is controlled, thereby making itpossible to prevent the image quality of a character portion which ison-screen displayed from being degraded.

The horizontal speed modulating signal control means may set theportion, corresponding to the graphic signal, in the horizontal speedmodulating signal generated by the horizontal speed modulating signalgenerating means at a predetermined level.

In this case, the portion, corresponding to the graphic signal, in thehorizontal speed modulating signal is set at a predetermined level.Consequently, the contour of the character portion is not enhanced. As aresult, the balance of the character portion which is on-screendisplayed is maintained.

The synthesizing and inverting means may comprise first synthesizingmeans for switching and outputting the video signal and the graphicsignal on the basis of a switching signal having a pulse correspondingto the position where the graphic signal is displayed, to synthesize thevideo signal and the graphic signal, and video signal inverting meansfor alternately inverting the output order of the video signal and thegraphic signal which have been synthesized by the first synthesizingmeans between the forward scanning and the backward scanning. Thehorizontal speed modulating signal control means may comprise switchingsignal inverting means for alternately inverting the switching signal onthe time axis between the forward scanning and the backward scanning,and control means for controlling a portion, corresponding to thegraphic signal, in the horizontal speed modulating signal generated bythe horizontal speed modulating signal generating means on the basis ofthe switching signal which has been inverted by the switching signalinverting means.

In this case, the video signal and the graphic signal are switched andoutputted on the basis of the switching signal having the pulsecorresponding to the position where the graphic signal is displayed, sothat the video signal and the graphic signal are synthesized. The outputorder of the video signal and the graphic signal which have beensynthesized is alternately inverted between the forward scanning and thebackward scanning. The, switching signal is alternately inverted on thetime axis between the forward scanning and the backward scanning.Further, the portion, corresponding to the graphic signal, in thehorizontal speed modulating signal is controlled on the basis of theinverted switching signal.

The horizontal speed modulating signal control means may furthercomprise pulse width expanding means for expanding the width of thepulse of the switching signal which has been inverted by the switchingsignal inverting means.

In this case, the width of the pulse of the switching signal isexpanded, thereby making it possible to reliably control the portion,corresponding to the graphic signal, in the horizontal speed modulatingsignal.

The pulse width expanding means may control the amount of expansion ofthe width of the pulse of the switching signal depending on thefrequency band of the horizontal speed modulating signal generated bythe horizontal speed modulating signal generating means.

In this case, the amount of expansion of the width of the pulse of theswitching signal is controlled depending on the frequency band of thehorizontal speed modulating signal. Accordingly, the portion,corresponding to the graphic signal, in the horizontal speed modulatingsignal can be reliably controlled depending on the frequency band of thehorizontal speed modulating signal.

The image display may further comprise binarizing means for binarizingthe switching signal and feeding the binarized switching signal to theswitching signal inverting means.

In this case, the switching signal is binarized. On the basis of thebinarized switching signal, the display of the video signal and thegraphic signal is switched, and the horizontal speed modulating signalis controlled.

The video signal inverting means may comprise first storing means forinputting and storing the video signal and the graphic signal,corresponding to the forward scanning, which have been outputted fromthe first synthesizing means as well as outputting the video signal andthe graphic signal which have been stored in the same order as that atthe time of the input, second storing means for inputting in apredetermined order and storing the video signal and the graphic signal,corresponding to the backward scanning, which have been outputted fromthe first synthesizing means as well as outputting the video signal andthe graphic signal which have been stored in an order reverse to that atthe time of the input, and second synthesizing means for synthesizingthe video signal and the graphic signal which are outputted from thefirst storing means and the video signal and the graphic signal whichare outputted from the second storing means. The switching signalinverting means may comprise third storing means for inputting in apredetermined order and storing the switching signal corresponding tothe forward scanning as well as outputting the stored switching signalin the same order as that at the time of the input, fourth storing meansfor inputting in a predetermined order and storing the switching signalcorresponding to the backward scanning as well as outputting the storedswitching signal in an order reverse to that at the time of the input,and third synthesizing means for synthesizing the switching signaloutputted from the third storing means and the switching signaloutputted from the fourth storing means.

In this case, the video signal and the graphic signal, corresponding tothe forward scanning, which have been synthesized are inputted to thefirst storing means in a predetermined order and stored therein, and thevideo signal and the graphic signal which have been stored in the firststoring means are outputted in the same order as that at the time of theinput. Further, the video signal and the graphic signal, correspondingto the forward scanning, which have been synthesized are inputted to thesecond storing means in a predetermined order and stored therein, andthe video signal and the graphic signal which have been stored in thesecond storing means are outputted in an order reverse to that at thetime of the input. The video signal and the graphic signal which areoutputted from the first storing means and the video signal and thegraphic signal which are outputted from the second storing means aresynthesized. The output order of the video signal and the graphic signalis thus alternately inverted between the forward scanning and thebackward scanning.

On the other hand, the switching signal corresponding to the forwardscanning is inputted to the third storing means in a predetermined orderand stored therein, and the switching signal which has been stored inthe third storing means is outputted in the same order as that at thetime of the input. Further, the switching signal corresponding to thebackward scanning is inputted to the fourth storing means in apredetermined order and stored therein, and the switching signal whichhas been stored in the fourth storing means is outputted in an orderreverse to that at the time of the input. The switching signal outputtedfrom the third storing means and the switching signal outputted from thefourth storing means are synthesized. The switching signal is thusalternately inverted on the time axis between the forward scanning andthe backward scanning.

The image display may further comprise format converting means forconverting the format of the inputted graphic signal into the format ofthe inputted video signal.

In this case, the format of the inputted graphic signal is convertedinto the format of the inputted video signal, so that the signals aresynthesized.

A horizontal speed modulator (horizontal velocity modulator) accordingto still another aspect of the present invention is a horizontal speedmodulator used for an image display for displaying an image by forwardscanning and backward scanning, comprising synthesizing and invertingmeans for alternately inverting the output order of a video signal and agraphic signal which are inputted between the forward scanning and thebackward scanning while synthesizing the video signal and the graphicsignal; horizontal speed modulating signal generating means fordifferentiating the video signal and the graphic signal which areoutputted from the synthesizing and inverting meals, to generate ahorizontal speed modulating signal; horizontal speed modulating meansfor performing horizontal speed modulation on the basis of thehorizontal speed modulating signal outputted from the horizontal speedmodulating signal generating means; and horizontal speed modulatingsignal control means for controlling a portion, corresponding to thegraphic signal, in the horizontal speed modulating signal generated bythe horizontal speed modulating signal generating means.

In the horizontal speed modulator, the output order of the video signaland the graphic signal which are inputted is alternately invertedbetween the forward scanning and the backward scanning while the videosignal and the graphic signal are being synthesized. The video signaland the graphic signal which have been synthesized are differentiated sothat the horizontal speed modulating signal is generated. The horizontalspeed modulation is performed on the basis of the horizontal speedmodulating signal.

In this case, the portion, corresponding to the graphic signal, in thehorizontal speed modulating signal is controlled, thereby making itpossible to prevent the image quality of the character portion which ison-screen displayed from being degraded.

The horizontal speed modulating signal generating means may comprisedifferentiating means for differentiating the video signal and thegraphic signal which are outputted from the synthesizing and invertingmeans, and polarity inverting means for alternately inverting thepolarity of an output signal of the differentiating means between theforward scanning and the backward scanning.

The horizontal speed modulating signal control means may set theportion, corresponding to the graphic signal, in the horizontal speedmodulating signal generated by the horizontal speed modulating signalgenerating means at a predetermined level.

In this case, the portion, corresponding to the graphic signal, in thehorizontal speed modulating signal is set at a predetermined level.Consequently, the contour of the character portion is not enhanced. As aresult, the balance of the character portion which is on-screendisplayed is maintained.

The synthesizing and inverting means may comprise synthesizing means forswitching and outputting the video signal and the graphic signal on thebasis of a switching signal having a pulse corresponding to the positionwhere the graphic signal is displayed, to synthesize the video signaland the graphic signal, and video signal inverting means for alternatelyinverting the output order of the video signal and the graphic signalwhich have been synthesized by the synthesizing means between theforward scanning and the backward scanning. The horizontal speedmodulating signal control means may comprise switching signal invertingmeans for alternately inverting the switching signal on the time axisbetween the forward scanning and the backward scanning, and controlmeans for controlling a portion, corresponding to the graphic signal, inthe horizontal speed modulating signal generated by the horizontal speedmodulating signal generating means on the basis of the switching signalwhich has been inverted by the switching signal inverting means.

In this case, the video signal and the graphic signal are switched andoutputted on the basis of the switching signal having the pulsecorresponding to the position where the graphic signal is displayed, sothat the video signal and the graphic signal are synthesized. The outputorder of the video signal and the graphic signal which have beensynthesized is alternately inverted between the forward scanning and thebackward scanning. The switching signal is alternately inverted on thetime axis between the forward scanning and the backward scanning.Further, the portion, corresponding to the graphic signal, in thehorizontal speed modulating signal is controlled on the basis of theinverted switching signal.

The horizontal speed modulating signal control means may furthercomprise pulse width expanding means for expanding the width of thepulse of the switching signal which has been inverted by the switchingsignal inverting means.

In this case, the width of the pulse of the switching signal isexpanded, thereby making it possible to reliably control the portion,corresponding to the graphic signal, in the horizontal speed modulatingsignal.

As described in the foregoing, according to the present invention, abidirectional deflection system image display capable of performingon-screen display is realized. Further, there is provided abidirectional deflection system image display capable of performingon-screen display and horizontal speed modulation. Particularly, theportion, corresponding to the graphic signal, in the horizontal speedmodulating signal is controlled, thereby making it possible to preventthe image quality of the character portion which is on-screen displayedfrom being degraded.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing the configuration of a principal partof an image display according to a first embodiment of the presentinvention.

FIG. 2 is a diagram showing an example of display of a video signal andan OSD graphic signal in bidirectional scanning and a phase relationshipamong a horizontal synchronizing signal, a video signal, a graphicsignal, and a display switching control signal at the time ofbidirectional scanning.

FIG. 3 is a block diagram showing the configuration of a principal partof an image display according to a second embodiment of the presentinvention.

FIG. 4 is a block diagram showing the configuration of a principal partof an image display according to a third embodiment of the presentinvention.

FIG. 5 is a diagram showing an example of display of a video signal andan OSD graphic signal in bidirectional scanning and a phase relationshipamong a horizontal synchronizing signal, a video signal, a graphicsignal, and a display switching control signal at the time ofbidirectional scanning.

FIG. 6 is a block diagram showing the configuration of a principal partof an image display according to a fourth embodiment of the presentinvention.

FIG. 7 is a block diagram showing the configuration of the whole of animage display according to a fifth embodiment of the present invention.

FIG. 8 is a block diagram showing the configuration of a video signalprocessing circuit, a speed modulating signal generating circuit and aspeed modulating signal control circuit shown in FIG. 7.

FIG. 9 is a block diagram showing the configuration of the speedmodulating signal generating circuit shown in FIG. 8.

FIG. 10 is a waveform diagram for explaining the operation of the imagedisplay shown in FIG. 8.

FIG. 11 is a waveform diagram for explaining the operation of the imagedisplay shown in FIG. 8.

FIG. 12 is a waveform diagram for explaining the operation of a secondconverting circuit shown in FIG. 8.

FIG. 13 is a diagram showing an example of display of a video signal andan OSD graphic signal in conventional bidirectional scanning and a phaserelationship among a horizontal synchronizing signal, a video signal, agraphic signal, and a display switching control signal at the time ofbidirectional scanning.

BEST MODE FOR CARRYING OUT THE INVENTION

(1) First Embodiment

FIG. 1 is a block diagram showing the configuration of a principal partof an image display according to a first embodiment of the presentinvention.

The image display shown in FIG. 1 comprises a video signal inverter 1, amicrocomputer 2, a CRT (Cathode-Ray Tube) 3, a graphic signal inverter4, a display signal switching device 5, and a switching control inverter6.

The video signal inverter 1 comprises an A/D (Analog-to-Digital)converter 101, a memory 102, and a D/A (Digital-to-Analog Converter)103. The graphic signal inverter 4 comprises an A/D converter 401, amemory 402, and a D/A converter 403. The switching control inverter 6comprises an A/D converter 601, a memory 602, and a D/A converter 603.

In the video signal inverter 1, the A/D converter 101 converts an analogvideo signal (image signal) VI1 fed from the exterior into a digitalvideo signal. The digital video signal obtained by the A/D converter 101is written into the memory 102 in a predetermined order and temporarilystored therein.

The video signal in a forward scanning period which has been stored inthe memory 102 is read out in the same order as that at the time of thewriting. On the other hand, the video signal in a backward scanningperiod which has been stored in the memory 102 is read out in an orderreverse to that at the time of the writing. The D/A converter 103converts the digital video signal which has been read out of the memory102 into an analog video signal VI2 and outputs the analog video signalVI2.

The output order of the video signal is thus inverted between theforward scanning period and the backward scanning period by the videosignal inverter 1.

The microcomputer 2 generates a video signal as well as a graphic signal(character signal) GI1 for performing on-screen display, and outputs adisplay switching control signal SW1. In the graphic signal inverter 4,the A/D converter 401 converts the analog graphic signal GI1 outputtedfrom the microcomputer 2 into a digital graphic signal. The digitalgraphic signal which has been obtained by the A/D converter 401 iswritten into the memory 402 in a predetermined order, and is temporarilystored therein.

The graphic signal in the forward scanning period which has been storedin the memory 402 is readout in the same order as that at the time ofthe writing. The graphic signal in the backward scanning period whichhas been stored in the memory 402 is read out in an order reverse tothat at the time of the writing. The D/A converter 403 converts thedigital graphic signal which has been read out of the memory 402 into ananalog graphic signal GI2 and output is the analog graphic signal GI2.

The output order of the graphic signal is inverted between the forwardscanning period and the backward scanning period by the graphic signalinverter 4.

In the display switching control device 6, the A/D converter 601converts the analog display switching control signal SW1 outputted fromthe microcomputer 2 into a digital display switching control signal. Thedisplay switching control signal obtained by the A/D converter 601 iswritten into the memory 602 in a predetermined order, and is temporarilystored therein.

The display switching control signal in the forward scanning periodwhich has been stored in the memory 602 is read out in the same order asthat at the time of the writing. The display switching control signal inthe backward scanning period which has been stored in the memory 602 isread out in an order reverse to that at the time of the writing. The D/Aconverter 603 converts the digital switching control signal which hasbeen read out of the memory 602 into an analog display switching controlsignal SW2, and outputs the analog display switching control signal SW2.

The output order of the display switching control signal is invertedbetween the forward scanning period and the backward scanning period bythe switching control inverter 6.

The display signal switching device 5 switches the video signal VI2outputted from the video signal inverter 1 and the graphic signal GI2outputted from the graphic signal inverter 4 on the basis of the displayswitching control signal SW2 outputted from the switching controlinverter 6, and outputs a display signal VO. The CRT 3 displays thedisplay signal VO outputted from the display signal switching device 5.

In the present embodiment, the video signal inverter 1 corresponds tovideo signal inverting means, the microcomputer 2 corresponds to graphicsignal generating means, the graphic signal inverter 4 corresponds tographic signal inverting means, the display signal switching device 5corresponds to display signal switching means, the switching controlinverter 6 corresponds to switching and inverting means, and the CRT 3corresponds to display means.

FIG. 2(a) is a diagram showing an example of display of a video signaland an OSD graphic signal in bidirectional scanning, and FIG. 2(b) is adiagram showing a phase relationship among a horizontal synchronizingsignal, a video signal, a graphic signal, and a display switchingcontrol signal at the time of the bidirectional scanning.

In FIG. 2(a), an ellipse on each of forward scanning lines L1 and L3 anda backward scanning line L2 indicates an on-screen display by thegraphic signal.

In FIG. 2(b), in the forward scanning period, the video signal VI2, thegraphic signal GI2, and the display switching control signal SW2 are notinverted on the time axis. In the backward scanning period, the videosignal VI2, the graphic signal GI2, and the display switching controlsignal SW2 are inverted on the time axis.

The video signal VI2 is outputted when the display switching controlsignal SW2 is at a low level, while the graphic signal GI2 is outputtedwhen the display switching control signal SW2 is at a high level.Display by the video signal VI2 as well as on-screen display by thegraphic signal GI2 are thus performed in the forward scanning period andthe backward scanning period.

According to the image display shown in FIG. 1, the on-screen display ispossible in the display of the video signal by bidirectional deflection.An image display such as a television receiver or a monitor apparatusfor display which comprises the function of on-screen displaying setcontents and channels is realized.

(2) Second Embodiment

FIG. 3 is a block diagram showing the configuration of a principal partof an image display according to a second embodiment of the presentinvention.

The image display shown in FIG. 3 comprises a video signal inverter 1 a,a microcomputer 2, a CRT 3, and a synthesizer 7. The operations of themicrocomputer 2 and the CRT 3 shown in FIG. 3 are the same as theoperations of the microcomputer 2 and the CRT 3 shown in FIG. 1.

The video signal inverter la comprises the memory 102 and the D/Aconverter 103 in the image display inverter 1 shown in FIG. 1. Thesynthesizer 7 comprises A/D converters 701 and 702 and a synthesizingcircuit 703.

In the synthesizer 7, the A/D converter 701 converts an analog videosignal VI1 fed from the exterior into a digital video signal. The A/Dconverter 702 converts an analog graphic signal GI1 outputted from themicrocomputer 2 into a digital graphic signal. The synthesizing circuit703 performs synthesis processing for replacing the digital video signaloutputted from the A/D converter 701 with the digital graphic signaloutputted from the A/D converter 702 when the graphic signal GI1 isoutputted from the microcomputer 2, and outputs a synthesized signalVG1.

The video signal inverter 1 a outputs the synthesized signal VG1 in aforward scanning period which is outputted from the synthesizer 7 as itis as a display signal VO, while inverting the synthesized signal VG1 ina backward scanning period on the time axis and outputting the invertedsynthesized signal VG1 as a display signal VO. The CRT 3 displays thedisplay signal VO outputted from the video signal inverter 1 a.

In the present embodiment, the microcomputer 2 corresponds to graphicsignal generating means, the synthesizer 7 corresponds to synthesizingmeans, the video signal inverter 1 a corresponds to video signalinverting means, and the CRT 3 corresponds to display means.

In the image display shown in FIG. 3, since the graphic signal which hasbeen synthesized with a video signal in the synthesizer 7 can bethereafter processed as a video signal, the synthesized signal VG1 inthe backward scanning period is inverted on the time axis by the videosignal inverter 1 a, as in the image display shown in FIG. 1, therebyobtaining the same result of processing as that in the image displayshown in FIG. 1.

(3) Third Embodiment

FIG. 4 is a block diagram showing the configuration of a principal partof an image display in a third embodiment of the present invention.

The image display shown in FIG. 4 comprises a video signal inverter 1, aCRT 3, a display signal switching device 5, a switching control inverter6, and a microcomputer 8. The configurations and the operations of thevideo signal inverter 1, the CRT 3, the display signal switching device5, and the switching control inverter 6 shown in FIG. 4 are the same asthe configurations and the operations of the video signal inverter 1,the CRT 3, the display signal switching device 5, and the switchingcontrol inverter 6 shown in FIG. 1.

Although the configuration of the microcomputer 8 shown in FIG. 4 is thesame as the configuration of the microcomputer 2 shown in FIG. 1, themicrocomputer 8 shown in FIG. 4 outputs a mask signal for masking avideo signal VI2 in place of a graphic signal GI1 when on-screen displayby a graphic signal is not performed. In the present embodiment, themask signal is a signal at a black level.

In the present embodiment, the video signal inverter 1 corresponds tovideo signal inverting means, the microcomputer 8 corresponds to graphicsignal generating means, the display signal switching device 5corresponds to display signal switching means, the switching controlinverter 6 corresponds to switching and inverting means, and the CRT 3corresponds to display means.

FIG. 5(a) is a diagram showing an example of display of a video signaland an OSD graphic signal in bidirectional scanning. FIG. 5(b) is adiagram showing a phase relationship among a horizontal synchronizingsignal, a video signal, a graphic signal, and a display switchingcontrol signal at the time of bidirectional scanning.

In FIG. 5(a), an ellipse on each of forward scanning lines L1 and L3indicates an on-screen display by the graphic signal. In a part of abackward scanning line L2 where the upper and lower forward scanninglines L1 and L3 are on-screen displayed, the signal at a black levelwhich is outputted from the microcomputer 8 is displayed.

In FIG. 5(b), in a forward scanning period, a video signal VI2, agraphic signal GI2, and a display switching control signal SW2 are notinverted on the time axis. In the forward scanning period, the videosignal VI2, the graphic signal GI2, and the display switching controlsignal SW2 are inverted on the time axis.

In the forward scanning period, the video signal VI2 is outputted whenthe display switching control signal SW2 is at a low level, while thegraphic signal GI2 is outputted when the display switching controlsignal SW2 is at a high level. On the other hand, in the backwardscanning period, the video signal VI2 is outputted when the displayswitching control signal SW2 is at a low level, while the signal at ablack level is outputted when the display switching control signal SW2is at a high level.

In the image display shown in FIG. 4, a part of the graphic signal isthe signal at a black level at the time of backward scanning.Consequently, in the forward scanning period, display by the videosignal VI2 as well as on-screen display by the graphic signal GI2 areperformed. In the backward scanning period, display by the video signalVI2 as well as display at a black level are performed.

In this example, although resolution in the on-screen display by thegraphic signal GI2 is lower than resolution in the display of the videosignal, a request for the resolution in the on-screen display is notmore strict than the resolution in the display of the video signal.Accordingly, no problems substantially arise.

(4) Fourth Embodiment

FIG. 6 is a block diagram showing the configuration of a principal partof an image display in a fourth embodiment of the present invention.

The image display shown in FIG. 6 comprises a video signal inverter 1 a,a microcomputer 2, a CRT 3, a switching control inverter 6, asynthesizer 7, and a masking circuit 9. The configurations and theoperations of the video signal inverter 1 a, the microcomputer 2, theCRT 3, and the synthesizer 7 shown in FIG. 6 are the same as theconfigurations and the operations of the video signal inverter 1 a, themicrocomputer 2, the CRT 3, and the synthesizer 7 shown in FIG. 3. Theconfiguration and the operation of the switching control inverter 6shown in FIG. 6 are the same as the configuration and the operation ofthe switching control inverter 6 shown in FIG. 1.

A synthesized signal VG1 outputted from the synthesizer 7 is fed to themasking circuit 9. The masking circuit 9 masks, in a case where parts ofupper and lower forward scanning lines are on-screen displayed, acorresponding part of a backward scanning line with a signal at a blacklevel at the time of backward scanning on the basis of a displayswitching control signal SW2 outputted from the switching controlinverter 6, and outputs a synthesized signal VG3.

The synthesized signal VG3 outputted from the masking circuit 9 is fedto the video signal inverter 1 a. The video signal inverter 1 a outputsthe synthesized signal VG3 in a forward scanning period as it is as adisplay signal VO, while inverting the synthesized signal VG3 in abackward scanning period on the time axis and outputting the invertedsynthesized signal VG3 as a display signal VO. The CRT 3 displays thedisplay signal VO outputted the video signal inverter 1 a.

In the present embodiment, the microcomputer 2 corresponds to graphicsignal generating means, the synthesizer 7 corresponds to synthesizingmeans, the masking circuit 9 corresponds to masking means, the videosignal inverter 1 a corresponds to video signal inverting means, and theCRT 3 corresponds to display means.

In the image display shown in FIG. 6, a part of the graphic signal is asignal at a black level at the time of the backward scanning, as in theimage display shown in FIG. 4. Consequently, display by the video signalas well as on-screen display by the graphic signal are performed in theforward scanning period, while display by the video signal as well asdisplay at a black level are performed in the backward scanning period.

(5) Fifth Embodiment

FIG. 7 is a block diagram showing the overall configuration of an imagedisplay in a fifth embodiment of the present invention.

The image display shown in FIG. 7 comprises a video signal processingcircuit 100, a synchronizing signal separating circuit 200, a speed(velocity) modulating signal generating circuit 300, a horizontal speed(velocity) modulating circuit 400, a horizontal deflecting circuit 500,a CRT 600, a high voltage output circuit 700, a vertical deflectingcircuit 800, and a speed (velocity) modulating signal control circuit900. A horizontal deflecting coil LH, a horizontal speed (velocity)modulating coil VMH, and a vertical deflecting coil LV are attached tothe CRT 600.

A video signal VI is fed to the video signal processing circuit 100 andthe synchronizing signal separating circuit 200. The video signalprocessing circuit 100 generates a display signal VO from the videosignal VI. The configuration and the operation of the video signalprocessing circuit 100 will be described later. The synchronizing signalseparating circuit 200 separates a horizontal synchronizing signal H anda vertical synchronizing signal V from the video signal VI.

The horizontal deflecting circuit 500 comprises a horizontal drivingcircuit, a horizontal output circuit, a distortion correcting circuit, alinearity correcting circuit, and an S-shaped capacitor. The horizontaldeflecting circuit 500 feeds a saw tooth horizontal deflecting currentfor deflecting an electron beam in the horizontal direction in the CRT600 to the horizontal deflecting coil LH in synchronization with thehorizontal synchronizing signal H outputted from the synchronizingsignal separating circuit 200.

The speed modulating signal generating circuit 300 generates a speed(velocity) modulating signal VM on the basis of the display signal VOoutputted from the video signal processing circuit 100. Theconfiguration and the operation of the speed modulating signalgenerating circuit 300 will be described later. The speed modulatingsignal control circuit 900 controls the speed modulating signal VMgenerated by the speed modulating signal generating circuit 300. Theconfiguration and the operation of the speed modulating signal controlcircuit 900 will be described later.

The horizontal speed modulating circuit 400 comprises a pre-drivingcircuit, a horizontal speed modulation driving circuit, and so forth,and feeds a horizontal speed (velocity) modulating current formodulating the speed of the electron beam in the horizontal direction inthe CRT 600 to the horizontal speed modulating coil VMH on the basis ofthe speed modulating signal VM outputted from the speed modulatingsignal generating circuit 300, and performs horizontal contourcorrection.

The high voltage output circuit 700 comprises a high voltage drivingcircuit, a flyback transformer, a dynamic automatic focusing controlcircuit, and a dynamic automatic focusing output circuit, and applies ahigh voltage to the CRT 600 in order to carry out focusing control orthe like.

The vertical deflecting circuit 800 comprises a vertical output circuit,and feeds all saw tooth vertical deflecting current for deflecting theelectron beam in the vertical direction in the CRT 600 to the verticaldeflecting coil LV in synchronization with the vertical synchronizingsignal V outputted from the synchronizing signal separating circuit 200.

FIG. 8 is a block diagram showing the configurations of the video signalprocessing circuit 100, the speed modulating signal generating circuit300, and the speed modulating signal control circuit 900 shown in FIG.7. FIG. 9 is a block diagram showing the configuration of the speedmodulating signal generating circuit 300 shown in FIG. 8.

The video signal processing circuit 100 shown in FIG. 8 comprises afirst converting circuit 11, a first synthesizing circuit 12, first andsecond memories 14 and 15, a second synthesizing circuit 18, a writingtiming generating circuit 20, and a reading timing generating circuit21. The speed modulating signal control circuit 900 comprises a secondconverting circuit 13, third and fourth memories 16 and 17, a thirdsynthesizing circuit 19, and a width generating circuit 22. The writingtiming generating circuit 20 and the reading timing generating circuit21 are common between the video signal processing circuit 100 and thespeed modulating signal control circuit 900.

The first converting circuit 11 converts the format of a graphic signal(character signal) gi into the format of the video signal VI, andoutputs the graphic signal GI. The first synthesizing circuit 12switches the video signal VI and the graphic signal GI outputted fromthe first converting circuit 11 on the basis of a display switchingcontrol signal SW11, and outputs a synthesized signal CI.

The second converting circuit 13 changes the display switching controlsignal SW11 into one bit (binarization), and outputs a 1-bit displayswitching control signal SW12.

The first and second memories 14 and 15 perform inversion processing forinverting the synthesized signal CI outputted from the firstsynthesizing circuit 12 on the time axis for each of a forward scanningperiod and a backward scanning period, and respectively outputsynthesized signals M1 and M2.

The third and fourth memories 16 and 17 perform inversion processing forinverting the display switching control signal SW12 outputted from thesecond converting circuit 13 on the time axis for each of the forwardscanning period and the backward scanning period, and respectivelyoutput display switching control signals M3 and M4.

The second synthesizing circuit 18 synthesizes the synthesized signal M1outputted from the first memory 14 and the synthesized signal M2outputted from the second memory 15, and outputs a display signal VO.

The third synthesizing circuit 19 synthesizes the display switchingcontrol signal M3 outputted from the third memory 16 and the displayswitching control signal M4 outputted from the fourth memory 17, andoutputs a display switching control signal SW13.

The writing timing generating circuit 20 feeds a writing timing signalto the first to fourth memories 14, 15, 16, and 17, and feeds a writingaddress signal WA to the first to fourth memories 14, 15, 16, and 17.

The reading timing generating circuit 21 feeds a reading timing signalto the first to fourth memories 14, 15, 16, and 17, and feeds a firstreading address signal RA1 to the first and third memories 14 and 16 andfeeds a second reading address signal RA2 to the second and fourthmemories 15 and 17. Further, the reading timing generating circuit 21feeds an inversion identifying signal INV to the second and thirdsynthesizing circuits 18 and 19, as well as the speed modulating signalgenerating circuit 300.

The width generating circuit 22 expands the pulse width of the displayswitching control signal SW13 outputted from the third synthesizingcircuit 19, and feeds a display switching control signal SW14 to thespeed modulating signal generating circuit 300.

As shown in FIG. 9, the speed modulating signal generating circuit 300comprises a differentiating circuit 231, an inverting circuit 232, and acontrol circuit 233.

The differentiating circuit 231 subjects the display signal VO tofirst-order differentiation, and outputs a differentiated signal DF1.The inverting circuit 232 inverts the polarity of the differentiatedsignal DF1 on the basis of the inversion identifying signal INV fed fromthe reading timing generating circuit 21, and outputs a differentiatedsignal DF2. The control circuit 233 generates a speed modulating signalVM from the differentiated signal DF2 on the basis of the displayswitching control signal SW14 fed from the width generating circuit 22.

In the present embodiment, the video signal processing circuit 100corresponds to synthesizing and inverting means, the CRT 600 correspondsto display means, the speed modulating signal generating circuit 300corresponds to horizontal speed modulating signal generating means, thehorizontal speed modulating circuit 400 and the horizontal speedmodulating coil VMH correspond to horizontal speed modulating means, andthe speed modulating signal control circuit 900 corresponds tohorizontal speed modulating signal control means. The first synthesizingcircuit 12 corresponds to first synthesizing means, the first and secondmemories 14 and 15 and the second synthesizing circuit 18 correspond tovideo signal inverting means, the third and fourth memories 16 and 17and the third synthesizing circuit 19 correspond to switching signalinverting means, and the control circuit 233 corresponds to controlmeans. Further, the width generating circuit 22 corresponds to pulsewidth expanding means, and the second converting circuit 13 correspondsto binarizing means. The first memory 14 corresponds to first storingmeans, the second memory 15 corresponds to second storing means, thesecond synthesizing circuit 18 corresponds to second synthesizing means,the third memory 16 corresponds to third storing means, the fourthmemory 17 corresponds to fourth storing means, and the thirdsynthesizing circuit 19 corresponds to third synthesizing means. Thefirst converting circuit 11 corresponds to format converting means.

FIGS. 10 and 11 are waveform diagrams for explaining the operation ofthe image display shown in FIG. 8. FIG. 12 is a waveform diagram forexplaining the operation of the second converting circuit 13 shown inFIG. 8. Referring now to the waveform diagrams of FIGS. 10, 11, and 12,the operation of the image display shown in FIG. 8 will be described.

In FIG. 8, the graphic signal gi is fed from a microcomputer (not shown)to the first converting circuit 11. In the first converting circuit 11,the format of the graphic signal gi is converted into the format of thevideo signal VI, and the graphic signal GI is outputted, as shown inFIG. 10. For example, when the video signal VI is composed of aluminance signal (Y) and chrominance difference signals (Pb) and (Pr),and the graphic signal gi is composed of an RGB (Red, Green, Blue)signal, the graphic signal gi is converted into a luminance signal and achrominance difference signal from the RGB signal by the firstconverting circuit 11.

In the first synthesizing circuit 12, the video signal VI and thegraphic signal GI are synthesized by methods such as weighted average onthe basis of the display switching control signal SW11, and thesynthesized signal CI is outputted, as shown in FIG. 10.

The synthesized signal CI outputted from the first synthesizing circuit12 is simultaneously written into the first and second memories 14 and15 in a predetermined order on the basis of the writing address signalWA outputted from the writing timing generating circuit 20. The writingof the synthesized signal CI into the first and second memories 14 and15 is controlled by the writing timing signal outputted from the writingtiming generating circuit 20.

In the example shown in FIG. 10, the writing address signal WA whichsuccessively increases from 0 to 767 is fed to the first and secondmemories 14 and 15.

The synthesized signal stored in the first memory 14 is read out in thesame order as that at the time of the writing on the basis of the firstreading address signal RA1 outputted from the reading timing generatingcircuit 21. The synthesized signal stored in the second memory 15 isread out in an order reverse to that at the time of the writing on thebasis of the second reading address signal RA2 outputted from thereading timing generating circuit 21. The reading of the synthesizedsignal from the first and second memories 14 and 15 is controlled by thereading timing signal outputted from the reading timing generatingcircuit 21.

In the example shown in FIG. 10, the first reading address signal RA1which successively increases from 0 to 767 is fed to the first memory14, and the second reading address signal RA2 which successivelydecrease from 767 to 0 is fed to the second memory 15.

The synthesized signal M1 shown in FIG. 10 which is delayed by onehorizontal scanning period from the synthesized signal CI is thusoutputted form the first memory 14. On the other hand, the synthesized,signal M2 shown in FIG. 10 which is delayed by one horizontal scanningperiod from the synthesized signal CI and is inverted on the time axisis outputted from the second memory 15.

The synthesized signal M2 corresponding to the backward scanning is thusinverted on the time axis, thereby making it possible to display a videosignal and a graphic signal in bidirectional deflection.

In the second synthesizing circuit 18, the synthesized signal M1outputted from the first memory 14 and the synthesized signal M2outputted from the second memory 15 are then synthesized on the basis ofthe inversion identifying signal INV shown in FIG. 10 outputted from thereading timing generating circuit 21, and the display signal VO isoutputted, as shown in FIG. 11. In the present embodiment, thesynthesized signal M1 outputted from the first memory 14 is selectedwhen the inversion identifying signal INV is at a high level, while thesynthesized signal M2 outputted from the second memory 15 is selectedwhen the inversion identifying signal INV is at a low level.

On the other hand, in the second converting circuit 13, the displayswitching control signal SW11 is binarized by being compared with thepredetermined reference level LV, so that the 1-bit display switchingcontrol signal SW12 is outputted, as shown in FIG. 12. In the exampleshown in FIG. 12, the display switching control signal SW12 enters a lowlevel when the level of the display switching control signal SW11 islower than the reference level LV, while entering a high level when thelevel of the display switching control signal SW11 is higher than thereference level LV.

The display switching control signal SW12 outputted from the secondconverting circuit 13 is simultaneously written into the third andfourth memories 16 and 17 in a predetermined order on the basis of thewriting address signal WA outputted from the writing timing generatingcircuit 20. The writing of the display switching control signal SW12into the third and fourth memories 16 and 17 is controlled by thewriting timing signal outputted from the writing timing generatingcircuit 20.

In the example shown in FIG. 10, the writing address signal WA whichsuccessively increase from 0 to 767 is fed to the third and fourthmemories 16 and 17.

The display switching control signal stored in the third memory 16 isread out in the same order as that at the time of the writing on thebasis of the first reading address signal RA1 shown in FIG. 10 which isoutputted from the reading timing generating circuit 21. The displayswitching control signal stored in the fourth memory 17 is read out inan order reverse to that at the time of the writing on the basis of thesecond reading address signal RA2 shown in FIG. 10 which is outputtedfrom the reading timing generating circuit 21. The reading of thedisplay switching control signal from the third and fourth memories 16and 17 is controlled by the reading timing signal outputted from thereading timing generating circuit 21.

In the example shown in FIG. 10, the first reading address signal RA1which successively increases from 0 to 767 is fed to the third memory16, and the second reading address signal RA2 which successivelydecreases from 767 to 0 is fed to the fourth memory 17.

The display switching control signal M3 shown in FIG. 11 which isdelayed by one horizontal scanning period from the display switchingcontrol signal SW12 shown in FIG. 10 is thus outputted from the thirdmemory 16. The display switching control signal M4 shown in FIG. 11which is delayed by one horizontal scanning period from the displayswitching control signal SW12 shown in FIG. 10 and is inverted on thetime axis is outputted from the fourth memory 17.

In the third synthesizing circuit 19, the display switching controlsignal M3 outputted from the third memory 16 and the display switchingcontrol signal M4 outputted from the fourth memory 17 are synthesized onthe basis of the inversion identifying signal INV outputted from thereading timing generating circuit 21, and the display switching controlsignal SW13 is outputted, as shown in FIG. 11.

The display switching control signal M3 outputted from the third memory16 is selected when the inversion identifying signal INV is at a level,while the display switching control signal M4 outputted from the fourthmemory 17 is selected when the inversion identifying signal INV is at alow level.

The pulse width of the display switching control signal SW13 outputtedfrom the third synthesizing circuit 19 is then expanded in the widthgenerating circuit 22, so that the display switching control signal SW14is outputted, as shown in FIG. 11.

In the differentiating circuit 231 in the speed modulating signalgenerating circuit 300 shown in FIG. 9, a first-order differential ofthe display signal VO which has been outputted from the secondsynthesizing circuit 18 is calculated, and the differentiated signal DF1is outputted. Further, in the inverting circuit 232, the polarity of thedifferentiated signal DF1 corresponding to the backward scanning periodis inverted on the basis of the inversion identifying signal INV, andthe differentiated signal DF2 is outputted. In the control circuit 233,a portion corresponding to a character portion of the differentiatedsignal DF2 is controlled at a predetermined level on the basis of thedisplay switching control signal SW14, and the speed modulating signalVM is outputted, as shown in FIG. 11. In the present embodiment, whenthe display switching control signal SW14 is at a high level, thedifferentiated signal DF2 is set at a zero level.

For example, the horizontal scanning speed is increased when the speedmodulating signal VM is positive, while being decreased when the speedmodulating signal VM is negative. As described above, the speedmodulating signal VM in a backward path is inverted on the time axis byinverting the video signal on the time axis and inverting the polarityof the differentiated signal. Consequently, horizontal speed modulationis also performed in the backward scanning.

The width generating circuit 22 shown in FIG. 8 controls the pulse widthof the display switching control signal SW14 depending on the frequencyband of the differentiated signal DF1 outputted from the differentiatingcircuit 231 shown in FIG. 9. Consequently, a portion, corresponding tothe graphic signal, in the speed modulating signal VM is reliably set ata zero level.

According to the image display shown in FIG. 8, the graphic signal isinverted on the time axis in the backward scanning, so that on-screendisplay possible in display of the video signal by the bidirectionaldeflection, and the speed modulating signal VM is invert on the timeaxis in the backward scanning, so that horizontal speed modulation ispossible. Consequently, the image quality is improved.

When the graphic signal is subjected to the horizontal speed modulation,a black part of an on-screen display looks thick, and a white partthereof looks thin. Consequently, the balance of the character portionis degraded, thereby degrading the image quality. In the image displayshown in FIG. 8, a portion, corresponding to the graphic signal, in thespeed modulating signal VM is controlled at a predetermined level, sothat the on-screen display is not subjected to the horizontal speedmodulation. Consequently, the image quality of the character portion isprevented from being degraded.

Although in the above-mentioned embodiment, the first and third memories14 and 16 are separately provided, and the second and fourth memories 15and 17 are separately provided, it is also possible to constitute thefirst and third memories 14 and 16 by one memory, store the synthesizedsignal CI and the display switching control signal SW12 at the sameaddress, constitute the second and fourth memories 15 and 17 by anotherone memory, and store the synthesized signal CI and the displayswitching control signal SW12 at the same address. Consequently, thenumber of memories can be reduced.

INDUSTRIAL APPLICABILITY

As described in the foregoing, an image display and a horizontal speedmodulator according to the present invention can be suitably used for amonitor apparatus, a television receiver, and so forth for a horizontalbidirectional modulation system display which displays a highly preciseimage.

What is claimed is:
 1. An image display for displaying an image byforward scanning and backward scanning, comprising: inverting means forinverting on the time axis a video signal and a graphic signal whichcorrespond to the backward scanning; switching and outputting means forswitching and outputting the video signal and the graphic signal whichcorrespond to the forward scanning and switching and outputting thevideo signal and the graphic signal, which have been inverted,corresponding to the backward scanning; and display means for displayingthe video signal and the graphic signal which have been outputted by theforward scanning and the backward scanning.
 2. An image display fordisplaying an image by forward scanning and backward scanning,comprising: video signal inverting means for alternately inverting theoutput order of an inputted video signal between the forward scanningand the backward scanning; graphic signal generating means forgenerating a graphic signal; graphic signal inverting means foralternately inverting the output order of the graphic signal generatedby said graphic signal generating means between the forward scanning andthe backward scanning; display signal switching means for switching thedisplay of the video signal outputted from said video signal invertingmeans and the graphic signal outputted from said graphic signalinverting means; switching and inverting means for alternately invertingthe order of switching by said display signal switching means betweenthe forward scanning and the backward scanning; and display means fordisplaying the video signal and the graphic signal which are outputtedfrom said display signal switching means by the forward scanning and thebackward scanning.
 3. An image display for displaying an image byforward scanning and backward scanning, comprising: synthesizing meansfor synthesizing a video signal and a graphic signal which correspond tothe forward scanning and the backward scanning; inverting means forinverting on the time axis the video signal and the graphic signal,which have been synthesized, corresponding to the backward scanning; anddisplay means for displaying by the forward scanning the video signaland the graphic signal, which have been synthesized, corresponding tothe forward scanning, and displaying by the backward scanning the videosignal and the graphic signal, which have been inverted, correspondingto the backward scanning.
 4. An image display for displaying an image byforward scanning and backward scanning, comprising: graphic signalgenerating means for generating a graphic signal; synthesizing means forsynthesizing an inputted video signal and the graphic signal outputtedfrom the graphic signal generating means; video signal inverting meansfor alternately inverting the output order of the video signal and thegraphic signal which have been synthesized by said synthesizing meansbetween the forward scanning and the backward scanning; and displaymeans for displaying the video signal and the graphic signal which areoutputted from said video signal inverting means by the forward scanningand the backward scanning.
 5. An image display for displaying an imageby forward scanning and backward scanning, comprising: inverting meansfor inverting on the time axis a video signal corresponding to thebackward scanning; switching and outputting means for switching andoutputting the video signal and the graphic signal which correspond tothe forward scanning; masking means for masking a portion, correspondingto a displayed portion of the graphic signal in the upper or lowerforward scanning, in the video signal corresponding to the backwardscanning; and display means for displaying by the forward scanning thevideo signal and the graphic signal which correspond to the forwardscanning, and displaying by the backward scanning the video signal,which has been partially masked, corresponding to the backward scanning.6. An image display for displaying an image by forward scanning andbackward scanning, comprising: video signal inverting means foralternately inverting the output order of an inputted video signal bythe forward scanning and the backward scanning; graphic signalgenerating means for generating a graphic signal; display signalswitching means for switching the display of the video signal outputtedfrom said video signal inverting means and the graphic signal outputtedfrom said graphic signal generating means as well as masking a portion,corresponding to a displayed portion of the graphic signal in the upperor lower forward scanning, in the video signal corresponding to thebackward scanning with a mask signal generated by said graphic signalgenerating means; switching and inverting means for alternatelyinverting the order of switching by said display signal switching meansbetween the forward scanning and the backward scanning; and displaymeans for displaying by the forward scanning the video signal and thegraphic signal which are outputted from said display signal switchingmeans, and displaying by the backward scanning the video signal and themask signal which are outputted from said display signal switchingmeans.
 7. An image display for displaying an image by forward scanningand backward scanning, comprising: synthesizing means for synthesizing avideo signal and a graphic signal which correspond to the forwardscanning and the backward scanning; masking means for masking a portion,corresponding to a displayed portion of the graphic signal in the upperor lower forward scanning, in the video signal corresponding to thebackward scanning; inverting means for inverting on the time axis thevideo signal, which has been partially masked, corresponding to thebackward scanning; and display means for displaying by the forwardscanning the video signal and the graphic signal which correspond to theforward scanning, and displaying by the backward scanning the videosignal, which has been partially masked, corresponding to the backwardscanning.
 8. An image display for displaying an image by forwardscanning and backward scanning, comprising: graphic signal generatingmeans for generating a graphic signal; synthesizing means forsynthesizing an inputted video signal and the graphic signal outputtedfrom the graphic signal generating means; masking means receiving thevideo signal and the graphic signal which have been synthesized by saidsynthesizing means, and masking a portion, corresponding to a displayedportion of the graphic signal in the upper or lower forward scanning, inthe video signal corresponding to the backward scanning and outputtingthe video signal and the graphic signal; video signal inverting meansfor alternately inverting the output order of the video signal and thegraphic signal which are outputted from said masking means between theforward scanning and the backward scanning; and display means fordisplaying by the forward scanning the video signal and the graphicsignal, corresponding to the forward scanning, which are outputted fromsaid video signal inverting means, and displaying by the backwardscanning the video signal, which has been partially masked, outputtedfrom said video signal inverting means.
 9. An image display fordisplaying an image by forward scanning and backward scanning,comprising: inverting means for alternately inverting the output orderof a video signal and a graphic signal between the forward scanning andthe backward scanning while synthesizing the video signal and thegraphic signal; display means for displaying the video signal and thegraphic signal which have been outputted by the forward scanning and thebackward scanning; generating means for generating a horizontal speedmodulating signal by differentiating the video signal and the graphicsignal which have been outputted; and horizontal speed modulating meansfor performing horizontal speed modulation on the basis of the generatedhorizontal speed modulating signal.
 10. The image display according toclaim 9, further comprising level control means for controlling aportion, corresponding to the graphic signal, in the horizontal speedmodulating signal generated by said generating means at a predeterminedlevel.
 11. An image display for displaying an image by forward scanningand backward scanning, comprising: synthesizing and inverting means foralternately inverting the output order of the video signal and thegraphic signal which are inputted between the forward scanning and thebackward scanning while synthesizing the video signal and the graphicsignal; display means for displaying the video signal and the graphicsignal which are outputted from said synthesizing and inverting means bythe forward scanning and the backward scanning; horizontal speedmodulating signal generating means for differentiating the video signaland the graphic signal which are outputted from said synthesizing andinverting means to generate a horizontal signal modulating signal; andhorizontal speed modulating means for performing horizontal speedmodulation on the basis of the horizontal speed modulating signaloutputted from said horizontal speed modulating signal generating means.12. The image display according to claim 11, wherein said horizontalspeed modulating signal generating means comprises differentiating meansfor differentiating the video signal and the graphic signal which areoutputted from said synthesizing and inverting means, and polarityinverting means for alternately inverting the polarity of an outputsignal of said differentiating means between the forward scanning andthe backward scanning.
 13. The image display according to claim 11,further comprising horizontal speed modulating signal control means forcontrolling a portion, corresponding to the graphic signal, in thehorizontal speed modulating signal generated by said horizontal speedmodulating signal generating means.
 14. The image display according toclaim 13, wherein said horizontal speed modulating signal control meanssets the portion, corresponding to the graphic signal, in the horizontalspeed modulating signal generated by said horizontal speed modulatingsignal generating means at a predetermined level.
 15. The image displayaccording to claim 13, wherein said synthesizing and inverting meanscomprises first synthesizing means for switching and outputting thevideo signal and the graphic signal on the basis of a switching signalhaving a pulse corresponding to the position where the graphic signal isdisplayed, to synthesize the video signal and the graphic signal, andvideo signal inverting means for alternately inverting the output orderof the video signal and the graphic signal which have been synthesizedby said first synthesizing means between the forward scanning and thebackward scanning, said horizontal speed modulating signal control meanscomprises switching signal inverting means for alternately invertingsaid switching signal on the time axis between the forward scanning andthe backward scanning, and control means for controlling a portion,corresponding to the graphic signal, in the horizontal speed modulatingsignal generated by said horizontal speed modulating signal generatingmeans on the basis of the switching signal which has been inverted bysaid switching signal inverting means.
 16. The image display accordingto claim 15, wherein said horizontal speed modulating signal controlmeans further comprises pulse width expanding means for expanding thewidth of said pulse of the switching signal which has been inverted bysaid switching signal inverting means.
 17. The image display accordingto claim 16, wherein said pulse width expanding means controls theamount of expansion of the width of the pulse of said switching signaldepending on the frequency band of the horizontal speed modulatingsignal generated by said horizontal speed modulating signal generatingmeans.
 18. The image display according to claim 15, further comprisingbinarizing means for binarizing said switching signal and feeding thebinarized switching signal to said switching signal inverting means. 19.The image display according to claim 15, wherein said video signalinverting means comprises first storing means for inputting and storingthe video signal and the graphic signal, corresponding to the forwardscanning, which have been outputted from said first synthesizing meansas well as outputting the video signal and the graphic signal which havebeen stored in the same order as that at the time of the input, secondstoring means for inputting in a predetermined order and storing thevideo signal and the graphic signal, corresponding to the backwardscanning, which have been outputted from said first synthesizing meansas well as outputting the video signal and the graphic signal which havebeen stored in an order reverse to that at the time of the input, andsecond synthesizing means for synthesizing the video signal and thegraphic signal which are outputted from said first storing means and thevideo signal and the graphic signal which are outputted from said secondstoring means, said switching signal inverting means comprises thirdstoring means for inputting and storing the switching signalcorresponding to the forward scanning in a predetermined order as wellas outputting the stored switching signal in the same order as that atthe time of the input, fourth storing means for inputting in apredetermined order and storing the switching signal corresponding tothe backward scanning as well as outputting the stored switching signalin an order reverse to that at the time of the input, and thirdsynthesizing means for synthesizing the switching signal outputted fromsaid third storing means and the switching signal outputted from saidfourth storing means.
 20. The image display according to claim 8,further comprising format converting means for converting the format ofthe inputted graphic signal into the format of the inputted videosignal.
 21. A horizontal speed modulator used for an image display fordisplaying an image by forward scanning and backward scanning,comprising: synthesizing and inverting means for alternately invertingthe output order of a video signal and a graphic signal which areinputted between the forward scanning and the backward scanning whilesynthesizing the video signal and the graphic signal; horizontal speedmodulating signal generating means for differentiating the video signaland the graphic signal which are outputted from said synthesizing andinverting means, to generate a horizontal speed modulating signal;horizontal speed modulating means for performing horizontal speedmodulation on the basis of the horizontal speed modulating signaloutputted from said horizontal speed modulating signal generating means;and horizontal speed modulating signal control means for controlling aportion, corresponding to the graphic signal, in the horizontal speedmodulating signal generated by said horizontal speed modulating signalgenerating means.
 22. The horizontal speed modulator according to claim1, wherein said horizontal speed modulating signal generating meanscomprises differentiating means for differentiating the video signal andthe graphic signal which are outputted from said synthesizing andinverting means, and polarity inverting means for alternately invertingthe polarity of an output signal of said differentiating means betweenthe forward scanning and the backward scanning.
 23. The horizontal speedmodulator according to claim 21, wherein said horizontal speedmodulating signal control means sets a portion, corresponding to thegraphic signal, in the horizontal speed modulating signal generated bysaid horizontal speed modulating signal generating means at apredetermined level.
 24. The horizontal speed modulator according toclaim 21, wherein said synthesizing and inverting means comprisessynthesizing means for switching and outputting the video signal and thegraphic signal on the basis of a switching signal having a pulsecorresponding to the position where the graphic signal is displayed, tosynthesize the video signal and the graphic signal, and video signalinverting means for alternately inverting the output order of the videosignal and the graphic signal which have been synthesized by saidsynthesizing means between the forward scanning and the backwardscanning, said horizontal speed modulating signal control meanscomprises switching signal inverting means for alternately invertingsaid switching signal on the time axis between the forward scanning andthe backward scanning, and control means for controlling a portion,corresponding to the graphic signal, in the horizontal speed modulatingsignal generated by said horizontal speed modulating signal generatingmeans on the basis of the switching signal which has been inverted bysaid switching signal inverting means.
 25. The horizontal speedmodulator according to claim 24, wherein said horizontal speedmodulating signal control means further comprises pulse width expandingmeans for expanding the width of said pulse of the switching signalwhich has been inverted by said switching signal inverting means.